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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P238
4-BIT SINGLE CHIP MICROCOMPUTER
DESCRIPTION
The PD75P238 is a version of the PD75238 in which the on-chip mask ROM is replaced by one-time PROM or EPROM. The one-time PROM version can be written to once only, and is useful for short-run and multiple deviceproduction of sets and early start-up. Also, the EPROM version allows programs to be written and rewritten, and is thus ideal for system evaluation. Functions are described in detail in the following User's Manual, which should be read when carrying out design work.
PD75238 User's Manual : IEU-731
The PD75P238 EPROM product does not provide a level of reliability suitable for use as a volume production product for users' devices. The EPROM product should be used solely for function evaluation in experiments of preproduction.
FEATURES
o PD75238 pin compatible o On-chip PROM: 32640 x 8 o On-chip RAM: 1024 x 4 o High-voltage display outputs . S0 to S8 & T0 to T9 : Internal pull-down resistors . S9, S16 to S23 & T10 to T15: Open-drain o Drive capability in same supply voltage range as mask version PD75238 (2.7 to 6.0 V) o Ports 4 & 5: No pull-up resistor o Port 7: No pull-down resistor Note USE VCR, Audio-visual, ECR, Microwave oven No internal pull-up and pull-down resistor function by mask option.
ORDERING INFORMATION
Ordering Code PD75P238GJ-5BG PD75P238KF Package 94-pin plastic QFP(s 20 mm) s 94-pin ceramic WQFN On-Chip ROM One-time PROM EPROM Quality Grade Standard Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. This manual describes common parts of One-time PROM and EPROM products as PROM.
The information in this document is subject to change without notice.
Document No. IC-2596A (O.D. No. IC-8014A) Date Published February 1994 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1992
PD75P238
PIN CONFIGURATION (TOP VIEW)
RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1
P10 /INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21
P22/PCL P23/BUZ P30/MD0
94 93 92919089 AN0 AVREF AVDD VDD VPP X2 X1 IC XT2 XT1 VSS S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
87 88 868584 8382 81807978777675747372 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 44 45 46 47 P32/MD2 P33/MD3 P40 P41 P42 P43 VSS P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 VDD
21 22 23 24 25262728 293031 3233 343536373839404142 43
T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152
Note
Ensure that power is supplied to the VDD and VSS pins (pins 4, 11, 30, 48, and 65). IC (Internally Connected) pins should be connected directly to VSS.
Remarks
2
PH3/T10/S15/P153 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
S4/P130
S5/P131 S6/P132
S7/P133 S8/P140 S9/P141 VDD VLOAD
P31/MD1
AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS
AN1
AN2 AN3
PD75P238GJ- 5BG
PD75P238KF
PD75P238
PIN NAME
P00 P10 P20 P30 P40 P50 P60 P70 to to to to to to to to P03 P13 P23 P33 P43 P53 P63 P73 : : : : : : : : : : : : : : : : : : : : Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11 Port12 Port13 Port14 Port15 PortH Digit Output Segment Output Positive Power Supply SCK0, SCK1 SO0, SO1 SI0, SI1 SB0, SB1 : : : : Serial Serial Serial Serial Clock I/O 0, 1 Data Output 0, 1 Data Input 0, 1 Bus I/O 0, 1
INT0, INT1, INT4 : External Vectored Interrupt Input 0, 1, 4 INT2 : External Test Input 2 PPO : Programmable Pulse Output TI0 : Timer Input 0 PTO0 BUZ PCL AN0 to AN7 AVREF AVDD AVSS X1, X2 XT1, XT2 RESET VPP MD0 to MD3 : : : : : : : : : : : : Programmable Timer Output 0 Buzzer Clock Programmable Clock Output Analog Input 0 to 7 Analog Reference Voltage Analog VDD Analog VSS Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Reset Programming Power Supply Mode Selection 0 to 3
P80 to P83 P90 to P93 P100 to P103 P110 to P113 P120 P130 P140 P150 to to to to P123 P133 P143 P153
PH0 to PH3 T0 to T15 S0 to S23 VDD VSS VLOAD
: Ground IC : Power Supply for FIP Driver
: Internally Connected
3
4
BASIC INTERVAL TIMER TIO TI0/P13 PTO0/P20 INTBT TIMER/EVENT COUNTER #0 INTT0 PROGRAM COUNTER (15) ALU CY SP (8) SBS (2) BANK PORT 2 PORT 3 PORT 4 PORT 5 INTW TIMER/ PULSE GENELATOR INTTPG SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SERIAL INTERFACE INTCSI SI1/P83 SO1/P82 SCK1/P81 fX / 2 INT0/P10 INT1/P11 INT2/P12 INT4/P00 8 TI0 AN0-AN3 AN4/P90-AN7/P93 AVDD AVREF AVSS PCL/P22 EVENT COUNTER PORT 10-15 A/D CONVERTER RESET VDD BIT SEQ. BUFFER(16) VSS VPP 24 XT1 XT2 X1 X2 VLOAD P100-P153 S16/P100-S23/P113 INTERRUPT CONTROL CLOCK OUTPUT CONTROL CLOCK DIVIDER
N
BLOCK DIAGRAM
PORT 0 PORT 1
4 4 4 4 4 4 4 4 4 4
P00-P03 P10-P13 P20-P23 P30/MD0 -P33/MD3 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93
BUZ/P23
WATCH TIMER GENERAL REG. ROM PROGRAM MEMORY 32640 x 8
PORT 6 DECODE AND CONTROL PORT 7 RAM DATA MEMORY 1024 x 4 PORT 8 PORT 9
PPO/P80
SERIAL INTERFACE
10 4 FIP CONTROLLER/ DRIVER 2 10
T0-T9 T10/S15/PH3/P153T13/S12/PH0/P150 T14/S11/ P143T15/S10/P142 S0/P120-S9/P141
CLOCK GENERATOR SUB MAIN
STAND BY CONTROL
CPU CLOCK
8
PD75P238
PD75P238
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name P00 P01
Input/Output
Dual-Function Pin INT4 SCK0
Function
8-Bit I/O
After Reset
Input/Output Circuit Type*1 B
Input P02 P03 P10 P11 Input P12 P13 P20 P21 Input/output P22 P23 PCL BUZ INT2 TI0 PTO0 -- SO0/SB0 SI0/SB1 INT0 INT1
4-bit input port (PORT0). Internal pull-up resistor specification by software is possible for P01 to P03 as a 3bit unit.
x
F -A Input F -B M -C
With noise elimination function 4-bit input port (PORT1). Internal pull-up resistor specification by software is possible as a 4-bit unit. x Input B -C
4-bit input/output port (PORT2). Internal pull-up resistor specification by software is possible as a 4-bit unit.
x
Input
E-B
P30 to P33 *2
Input/output
MD0 to MD3
Programmable 4-bit input/output port (PORT3). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. N-ch open-drain 4-bit input/output port (PORT4). Data input/output pins for program memory write/verify (low-order 4 bits).
x
Input
E-C
P40 to P43 *2
Input/output
--
Input
M-A
P50 to P53 *2
Input/output
--
N-ch open-drain 4-bit input/output port (PORT5). Data input/output pins for program memory write/verify (high-order 4 bits).
Input
M-A
P60 to P63
Input/output
--
Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
E-C
P70 to P73
Input/output
--
4-bit input/output port (PORT7).
Input
E
*
1. A circle denotes Schmitt-triggerd input. 2. Direct LED drive capability
5
PD75P238
1.1
PORT PINS (2/2)
Pin Name P80 P81 P82 P83 P90 to P93 P100 to P103 P110 to P113
Input/Output Input/output Input/output Input/output Input Input Output Output
DualFunction Pin PPO SCK1
Function
8-Bit I/O
After Reset
Input/Output Circuit Type*1 A F
4-bit input port (PORT8). SO1 SI1 AN4 to AN7 S16 to S19 S20 to S23 4-bit input port (PORT9). P-ch open-drain 4-bit high-voltage output port. P-ch open-drain 4-bit high-voltage output port. P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistors.
x
Input E B
x
Input High impedance
Y-A
I-D
P120 to P123
Output
S0 to S3
I-E VLOAD level
P130 to P133
Output
S4 to S7
P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistors.
I-E
P140
S8 P-ch open-drain 4-bit high-voltage output port. Internal pull-down resistor on P140 only.
VLOAD level
I-E
P141 P142*2 P143*2 P150*2 P151*2
Output
S9 S10/T15 S11/T14 S12/T13/PH0 S13/T12/PH1
I-D
High impedance
Output P152*2 P153*2 PH0 PH1 PH2 PH3 Output S14/T11/PH2 S15/T10/PH3 S12/T13/P150 S13/T12/P151
P-ch open-drain 4-bit high-voltage output port.
I-D
P-ch open-drain 4-bit high-voltage output port. S14/T11/P152 S15/T10/P153
x
High impedance
I-D
*
1. A circle denotes Schmitt-triggerd input. 2. Direct LED drive capability.
6
PD75P238
1.2
NON-PORT PINS (1/2)
Pin Name PPO TI0 PTO0 PCL BUZ SCK0 SO0/SB0
Input/Output Output Input Output Output Output Input/output Input/output
DualFunction Pin P80 P13 P20 P22 P23 P01 P02
Function Timer/pulse generator pulse output pin. External event pulse input pin for timer/event counter #0 or event counter #1. Timer/event counter output pin. Clock output pin. Fixed-frequency output pin (for buzzer or system clock trimming use). Serial clock input/output pin. Serial data output pin. Serial bus input/output pin. Serial data input pin. Serial bus input/output pin. Edge-detected vectored interrupt input pin (either rising or falling edge detection).
After Reset Input
Input/Output Circuit Type* A B -C
Input Input Input Input Input
E-B E-B E-B F -A F -B
SI0/SB1
Input/output
P03
Input
M -C
INT4
Input
P00
B
INT0 Input INT1 INT2 SCK1 SO1 SI1 AN0 to AN3 Input AN4 to AN7 AVREF AVDD AVSS Input Input Input/output Output Input
P10
Edge-detected vectored interrupt input pin (detected edge selectable).
Clocked B -C Asynchronous
P11 P12 P81 P82 P83 Edge-detection testable input pin (rising edge detection). Serial clock input/output pin. Serial data output pin. Serial data input pin.
Asynchronous Input Input Input
B -C F E B Y
A/D converter analog input pin. P90 to P93 A/D converter reference voltage input pin. A/D converter power supply pin. A/D converter reference GND potential pin. Main system clock oscillation crystal/ceramic resonator input. When an external clock is used, the clock is input to X1 and the inverted clock to X2. Subsystem clock oscillation crystal resonator input. When an external clock is used, the clock is input to XT1 and XT2 is left open. System reset input pin. P30 to P33 Mode selection pin for program memory write/verify. Internally Connected . Connect to VSS directly. Program voltage application pin for program memory write/verify . Connected to VDD in normal operation. Applies +12.5 V in program memory write/verify. B E-C Y-A Z
X1, X2
Input
XT1 XT2 RESET MD0 to MD3 IC
Input
Input Input
5
VPP
*
A circle denotes Schmitt-triggerd input.
7
PD75P238
1.2
NON-PORT PINS (2/2)
Pin Name VDD (3 pins) VSS (2 pins) VLOAD
Input/Output
DualFunction Pin
Function Positive power supply pins. Apply +6 V in PROM write/verify. Ground potential pin. FIP controller/driver pull-down resistor connection/ power supply pin. Digit output high-voltage large large-current output pins.
After Reset
Input/Output Circuit Type
I-D VLOAD level High impedance
T0 to T9 *
I-E
T10/S15 to T13/S12 T14/S11 T15/S10 S0 to S3 * Output S4 to S7 *
PH3/P153 to PH0/P150 P143 P142 P120 to P123
Digit/segment output dual-function high-voltage largecurrent output pins. Unused pins usable as Port H. Usable as Port 15 in static mode. Digit/segment output dual-function high-voltage largecurrent output pin. Usable as Port 14 in static mode.
I-D
High impedance VLOAD level VLOAD level
I-D
I-E
P130 to P133 Segment high-voltage output pins. Usable as Port 12 to Port 14 in static mode.
I-E
S8 *
P140
VLOAD level High impedance High impedance
I-E
S9
P141
I-D
S16 to S19
P100 to P103 Segment high-voltage output pins. Usable as Port 10 & Port 11 in static mode.
I-D
S20 to S23
P110 to P113
High impedance
I-D
*
Internal pull-down resistor
8
PD75P238
1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pins are shown in Fig. 1-1 in partially simplified form. Fig. 1-1 Pin Input/Output Circuits (1/3) TYPE A
VDD data P-ch IN N-ch output disable N-ch P-ch OUT
TYPE D
VDD
CMOS Standard Input Buffer TYPE B
Push-Pull Output with High Impedance Output Capability (P-ch and N-ch both OFF) TYPE E
data Type D output disable
IN/OUT
IN
Type A
Schmitt-Triggered Input with Hysteresis Characteristics TYPE B-C
VDD P.U.R. P.U.R. enable
Input/Output Circuit Composed of Type D Push-Pull Output and Type A Input Buffer TYPE E-B
VDD P.U.R. output disable data Type D output disable P-ch
P-ch
IN/OUT
IN
Type A
P.U.R. : Pull-Up Resistor
Schmitt-Triggered Input with Hysteresis Characteristics
P.U.R.:Pull-Up Resistor
9
PD75P238
Fig. 1-1 Pin Input/Output Circuits (2/3)
TYPE E-C TYPE F-B
P.U.R. P.U.R. enable data Type D output disable P-ch
output disable (P-ch) data output disable output disable (N-ch)
Type B
VDD
VDD P.U.R. P.U.R. enable VDD P-ch P-ch
IN/OUT
IN/OUT
N-ch
Type A
P.U.R.:Pull-Up Resistor
P.U.R.:Pull-Up Resistor
TYPE F
TYPE F-C
VDD
data Type D output disable IN/OUT
P.U.R. P.U.R. enable data P-ch
IN/OUT Type D
Type B
output disable
Type B
Input /Output Circuit Composed of Type D PushPull Output and Type B Schmitt-Triggered Input
TYPE F-A
VDD P.U.R. P.U.R. enable data Type D output disable P-ch
P.U.R.:Pull-Up Resistor
TYPE I-D
VDD data P-ch
VDD P-ch OUT
IN/OUT
N-ch
Type B
P.U.R.:Pull-Up Resistor
10
PD75P238
Fig. 1-1 Pin Input/Output Circuits (3/3)
TYPE I-E TYPE Y
VDD data P-ch
VDD
P-ch AVDD
P-ch OUT P.D.R
IN Sampling C AVSS
+ AVSS
AVDD
N-ch
N-ch
VLOAD
AVSS
P.D.R: Pull-Down Resistor
Reference Voltage (From Series Resistance String Voltage Tap)
TYPE M-A
TYPE Y-A
IN/OUT
data output disable
N-ch
P-ch IN Sampling C AVSS AVDD
+ AVSS
AVDD
N-ch
Middle-High Voltage Input Buffer
AVSS
P.U.R: Pull-Up Resistor
P.U.R.:Pull-Up Resistor
Reference Voltage (From Series Resistance String Voltage Tap)
TYPE M-C
VDD P.U.R. P.U.R. enable P-ch IN/OUT
TYPE Z
data output disable
Type B
N-ch
AVSS
P.U.R: Pull-Up Resistor P.U.R.:Pull-Up Resistor
11
PD75P238
1.4
DISPOSITION OF UNUSED PIN Table 1-2 Recommended Commection of Unused Pins (1/2)
Pin P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0 to P12/INT2 Connect to VSS. P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to PPO Input state : Output state : Connect to VSS or VDD. Leave open. Connect to VSS or VDD. Recommended Connection Connect to VSS.
P81 to SCK1 Connect to VSS or VDD. P82/SO1 P83/SI1 P90/AN4 to P93/AN7 Connect to VSS.
12
PD75P238
Table 1-2 Recommended Commection of Unused Pins (2/2)
Pin P100/S16 to P103/S19 P110/S20 to P113/S23 P120 to P123 Leave open. P130 to P133 P140 to P143 P150 to P153 AN0 to AN3 Connect to VSS. AVREF AVDD AVSS XT1 XT2 VLOAD IC Connect to VDD. Connect to VSS. Connect to VSS or VDD. Leave open. Connect to VSS or leave open. Connect to VSS. Recommended Connection
5
13
PD75P238
2. DIFFERENCES BETWEEN PD75P238 AND PD75238
The PD75P238 is a product with the program memory of the PD75238 using on-chip mask ROM replaced by one-time PROM or EPROM. Table 2-1 shows differences between PD75P238 and PD75238. The differences between these products must be thoroughly checked when, for example, switching from use of PROM for application system debugging and reproduction to use of a mask ROM product for volume production. For details of CPU function and on-chip hardware, refer to the document "PD75238 User's Manual" (IEU-731). Table 2-1 Differences between PD75P238 and PD75238
Product Name
Parameter ROM RAM FIP controller/ driver Pull-up resistors
PD75238
Mask ROM 32K x 8 1K x 4
PD75P238
One-time PROM, EPROM 32K x 8
No. of segments No. of digits Ports 4 & 5 Port 7 S0 to S8 S9 Mask option
9 to 24 9 to16 No No On-chip No No On-chip No VDD P30 to P33 VPP P30/MD0 to P33/MD3
Pull-down resistors
S16 to S23 T0 to T9 T10 to T15 Pin 5
Pin connection Pins 70 to 73
5
Electrical specifications
The mask ROM products and PROM products have different consumption currents, operating temperature range etc. See the Electrical Specifications section in the relevant Data Sheet for details. 2.7 to 6.0 V Mask option 94-pin plastic QFP (s 20 mm) s On-chip 94-pin plastic QFP (s 20 mm) s 94-pin ceramic WQFN
Operating supply voltage range Subsystem clock feedback resistor Package
5
Others
The mask ROM products and PROM products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation.
5
Note
Noise resistance and noise radiation differs between the PROM products and mask ROM products.
When investigating a switch from preproduction to volume production, throughout evaluation should be carried out with the mask ROM CS product (not the ES product).
14
PD75P238
3. PROGRAM MEMORY (PROM)
The program memory is PROM with a 32640 x 8-bit configuration wich stores program and table tata etc. The program memory is addressed by the program counter. In addition, table data can be referenced by a table referencing instruction (MOVT). The rage of address to which branch instructions and subroutine call instructions and subroutine call instructions and subroutine call instructions can branch is shown in Fig. 3-1. The entire space comprising 0000H to 7F7FH can be directly branched to by the entire-space branch instruction (BRA !addr1) and the entire-space call instruction (CALLA !addr1). The relative branch instruction (BR $addr) allows branching to addresses [PC contents -15 to -1 and +2 to +16] irrespective of block boundaries. In addition, the following addresses are specially allocated (except for 0000H and 0001H, the entire area can be used as ordinary program memory). * Addresses 0000H & 0001H Vector table to which the program start address and MBE & RBE set value upon RESET input are written. Reset servicing can be started from any address in the 16K (000H to 3FFFH). * Addresses 0002H to 000FH Vector table to which the program start address and MBE & RBE set value for the various vectore interrupts are written. Interrupt servicing can be started from any address in the 16K space (0000H to 3FFFH). * Addresses 0020H to 007FH Table area referenced by GETI instruction*. * The GETI instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as 1 byte, and is used to reduce the number of program steps.
15
PD75P238
Fig. 3-1 Program Memory Map
7 0000H 0002H 0004H 0006H 6
Internal Reset Start Address (High-Order 6 Bits) (Low-Order 8 Bits)
0
MBE RBE
MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
MBE RBE INT0 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
BRA !addr Instruction Branch Address
MBE RBE INT1 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits) BR !addr Instruction Branch Address
CALLA !addr Instruction Branch Address
0008H
MBE RBE INTSO Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
000AH
MBE RBE INTT0 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
CALLF ! faddr Instruction Entry Address
000CH
MBE RBE INTTPG Start Address (High-Order 6 Bits)
(Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address
CALL !addr Instruction Branch Address
BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16)
000EH
MBE RBE
INTKS Start Address (High-Order 6 Bits) (Low-Order 8 Bits)
0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH 6000H 6FFFH 7000H 7F7FH
GETI Instruction Reference Table

BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address BRCB !caddr instruction Branch Address
Branch/Call Addresses by GETI

Note
The above interrupt vector start addresses are 14-bit, and thus should be set in the 16K space
(0000H to 3FFFH). Remarks In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses with the low-order 8 bits only of the PC modified.
16
PD75P238
4. STACK BANK SELECTION REGISTER (SBS)
The stack bank selection register specifies one memory bank from memory banks 0 to 3 as the stack area.Its format is shown in Fig. 4-1. The stack bank selection register is set by a 4-bit memory manipuration instruction. On RESET input bit only is set to "1" and the remaining bits are undefined. Therefore this register must always be initialized to 00xxB* at the start of a program. Fig. 4-1 Stack Bank Selection Register Format
Address F84H
3
2
1
0
Symbol SBS
SBS3 SBS2 SBS1 SBS0
Stack Area Specification
0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
0
0
Ensure that 0 is written to bits 2 & 3.
Note After RESET input a subroutine call instruction and interrupt enabling instruction should be executed after setting the stack bank selection register. * xx should be set to the desired value.
17
PD75P238
5. PROGRAM MEMORY WRITE AND VERIFY OPERATIONS
The program memory incorporated in the PD75P238 is 32640 x 8-bit electrically writable PROM. Write/verify operations on this PROM are executed using the pins shown in the table below. Address updating is performed by means of clock input from the X1 pin rather than by address input.
Table 5-1 Pins Used for Program Memory Write/Verify
Pin Name
Function
VPP
Voltage applecation pin for program memory write/verify (normally VDD potential).
X1, X2
Address update clock input for program memory write/verify. Inverse of X1 pin signal is input to X2 pin.
MD0 to MD3
Operating mode selection pin for program memory write/verify.
P40 to P43 (low-order 4 bits) P50 to P53 (high-order 4 bits)
8-bit data input/output pin for progrm memory write/verify. Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify.
VDD
Note
1.
Pins not used in a program memory write/verify operation are handled as follows: Ports 0 to 2, ports 6 to 15 T0 to T9, AN0 to AN3, XT1
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Connect to GND
VLOAD, AVREF, AVSS, RESET AVDD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Connect to VDD XT2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Leave open 2. On the PD75P238KF which is equipped with an erase window the shading cover film should be attached except when performing EPROM erasure. 3. Since the PD75P238GJ one-time PROM version is not provided with an erase window, program memory contents cannot be erased.
18
PD75P238
5.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P238 enters the program memory write/ verify mode. This mode comprises one of the operating modes shown in Table 5-2 according to the setting of pins MD0 to MD3.
Table 5-2 Program Memory Write/Verify Operating Modes
Operating Mode Setting Operating Mode VPP VDD MD0 MD1 MD2 MD3
H
L
H
L
Program memory address zero-clear
L + 12.5 V +6V L
H
H
H
Write mode
L
H
H
Verify mode
H
x
H
H
Program inhibit mode
Remarks
x : L or H
19
PD75P238
5.2 PROGRAM MEMORY WRITE PROCEDURE The procedure for writing to program memory is as shown below, allowing high-speed writing. (1) Unused pins are connected to VSS. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 10 s wait. Program memory address zero-clear mode. 6V is supplied to VDD, 12.5 V to VPP. Program inhibit mode. Data is written in 1 ms write mode. Program inhibit mode. Verify mode. If write is successful go to (10), otherwise repeat (7) to (9). (Number of times written in (7) to (9): X) x 1 ms additional writes. Program inhibit mode. Program memory address is updated (+1) by inputting 4 pulses to the X1 pin. Steps (7) to (12) are repeated until the last address. Program memory address zero-clear mode.
(15) VDD / VPP pin voltage is changed to 5 V. (16) Power-off. Steps (2) to (12) of this procedure are shown in Fig. 5-1.
Fig. 5-1 Program Memory Write Timing
Repeated X Times
Write
Verify
Additional Write
Address Increment
VPP VDD VDD + 1 VDD VDD
Data Output
P40 to P43
0 to P53
MD0 (P30)
Data Input
X1
VPP
Data Input
MD1 (P31) MD2 (P32) MD3 (P33)
20

PD75P238
5.3 PROGRAM MEMORY READ PROCEDURE PD75P238 program memory contents can be read using the following procedure. Reading is performed in verify mode. (1) Unused pins are connected to VSS. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) 10 s wait. (4) (5) (6) (7) Program memory address zero-clear mode. 6 V supplied to VDD, and 12.5 V to VPP. Program inhibit mode. Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per
4-pulse-input cycle. (8) Program inhibit mode. (9) Program memory address zero-clear mode. (10) VDD / VPP pin voltage is changed to 5 V. (11) Power-off. Steps (2) to (9) of this procedure are shown in Fig. 5-2.
Fig. 5-2 Program Memory Read Timing
VPP VPP
VDD
VDD +1 VDD VDD X1 P40 to P43 P50 to P53
Data Output
Data Output
MD0 (P30)
(P31)
MD2 (P32)
MD3 (P33)
MD1
"L"

21
PD75P238
5.4
ERASURE (PD75P238KF ONLY)
The Programmed data contents of the PD75P238KF can be erased by exposure to ultraviolet light through the window in the top. The ultraviolet wave length which effects erasure is 250 nm, and the quantity of radiation necesary for complete erasure is 15 W*s/ cm2 (ultraviolet radiation intensity x erasure time). Using a commercially available ultraviolet lamp (254 nm vavelength, 12 mW/cm 2 intensity) erasure can be accomplished in approximately 15 to 20 minutes. Note 1. Memory contents may also be erased by prolonged exposure to direct sunlight fluorescent lighting. To protect the contents ensure that the top window is masked with the shading cover film. The shading cover film supplied with NEC's UV EPROM products should be used. 2. When carrying out erasure the distance between the ultraviolet lamp and the PD75P238KF should normally be no greater than 2.5 cm. Remarks A longer erasure time may be required if there is deterioration of the ultraviolet lamp, or if the package window is not clean, etc.
22
PD75P238
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
PARAMETER SYMBOL VDD Supply voltage VLOAD VPP VI1 Input voltage VI2 VO Output voltage VOD Display output pins 1 pin except display output pins S0 to S9, S16 to S23 1 pin Output current high IOH T0 to T15 1 pin All pins except display output pins All display output pins Peak value 1 pin Effective value Peak value Output current low IOL* Total of port 0, 2, 3, 4 Effective value Peak value Total of port 5 to 8 Effective value Operating temperature Storage temperature Topt 60 -40 to +70 mA C C 60 100 mA mA 15 100 mA mA VDD -40 to VDD +0.3 -15 -15 -30 -30 -120 30 V mA mA mA mA mA mA Ports 4, 5 Open-drain -0.3 to +11 -0.3 to VDD +0.3 V V Except ports 4, 5 TEST CONDITIONS RATING -0.3 to +7.0 VDD -40 to VDD +0.3 -0.3 to +13.5 -0.3 to VDD +0.3 UNIT V V V V
Pins except display output pins
Tstg
-65 to +150
*
The Effective value should be calculated as follows. [Effective value] = [Peak value] x
Duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute ratings are not exceeded.
5
23
PD75P238
OPERATING SUPPLY VOLTAGE RANGE (Ta = -40 to +70 C)
PARAMETER CPU*1 Display controller Timer/pulse generator Other hardware*1 TEST CONDITIONS MIN. *2 4.5 4.5 2.7 MAX. 6.0 6.0 6.0 6.0 UNIT V V V V
* 1. 2.
Except the system clock oscillator, display controller and timer/pulse generator. The operating power supply voltage range varies depending on the cycle time. Refer to the section describing AC characteristics.
24
PD75P238
MAIN SYSTEM CLOCK RESONATOR CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V)
RESONATOR
RECOMMENDED CHARACTERISTICS
PARAMETER Oscillator frequency (fx)*1
TEST CONDITIONS VDD = Oscillator voltage range After VDD has reached MIN. value of oscillator voltage range.
MIN.
TYP.
MAX.
UNIT
2.0
6.2
MHz
X1
X2
Ceramic resonator
C1 C2
Oscillation stabilization time*2
4
ms
X1
X2
Oscillator frequency (fx)*1 VDD = 4.5 to 6.0 V
2.0
4.19
6.2
MHz
Crystal resonator
C1 C2
Oscillation stabilization time*2
10
ms
30
ms
X1
X2
X1 input frequency (fx)*1
2.0
6.2
MHz
External Clock
PD74HCU04
X1 input high and low level width (tXH, tXL)
81
250
ns
* 1. Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC characteristics for the instruction execution time. 2. Oscillation stability time is time required for oscillation to stabilize after VDD has reached the MIN. value in oscillation voltage range or STOP mode has been released. Note When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines caring a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator.
5
25
PD75P238
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V)
RESONATOR
RECOMMENDED CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
XT1
XT2 R
Oscillator frequency (fXT)*1 VDD = 4.5 to 6.0 V Oscillation stabilization time*1
32
32.768
35
kHz
Crystal resonator
C3
1.0
2
s
C4
10
s
XT1 input frequency (fXT)*1
XT1 XT2
32
100
kHz
External Clock X1 input high and low level width (tXTH, tXTL) 5 15
s
* 1. 2.
Oscillator frequency and input frequency indicate oscillator characteristics only. Refer to the AC characteristics for the instruction execution time. Oscillation stability time is time required for oscillation to stabilize after VDD has reached the MIN. value in oscillation voltage range. When subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines caring a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system, clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.
5
Note
CAPACITANCE (Ta =25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance (Output except display output) Input/output capacitance Output capacitance (Display output) SYMBOL CI CO CIO CO f = 1 MHz 0 V for pins except measured pins TEST CONDITIONS MIN. TYP. MAX. 15 15 15 35 UNIT pF pF pF pF
26
PD75P238
RECOMMENDED OSCILLATOR CONTANTS MAINSYSTEMCLOCK : CERAMIC RESONATOR (Ta = - 40 to + 85 C)
RECOMMENDED OSCILLATOR CONSTANTS(pF) C1 C2 30 - 30 - 30 - 30 - 30 - 30 - 4.0 6.0 3.3 6.0 3.0 6.0 2.7 6.0 OSCILLATOR VOLTAGE RANGE(V) MIN. MAX.
MAUNFACTURER
PRODUCT NAME
FREQUENCY (MHz)
REMARKS
---------------------------CST2.0MG CSA2.5MG093
CSA2.0MG
2.0
-------------------------- 30 - 30 - 30 - 30 - 30 -
30
--------------------------------------On-chip capacitor product
---------------------------CST2.5MGW093 CSA4.19MGU
2.5
--------------------------
--------------------------------------On-chip capacitor product
Murata Mfg.
---------------------------CST4.19MGWU CSA2.5MG
4.19
--------------------------
--------------------------------------On-chip capacitor product
---------------------------CST2.5MGW CSA4.19MG
2.5
--------------------------
--------------------------------------On-chip capacitor product
---------------------------CST4.19MGW CSA6.0MG
4.19
--------------------------
--------------------------------------On-chip capacitor product
---------------------------CST6.0MGW
6.00
--------------------------
--------------------------------------On-chip capacitor product
MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = - 20 to + 70 C)
RECOMMENDED OSCILLATOR CONSTANTS(pF) C1 Kinseki, Ltd. HC-49/U-S 3.072 to 6.000 22 C2 22 OSCILLATOR VOLTAGE RANGE(V) MIN. 4.0 MAX. 6.0
MAUNFACTURER
PRODUCT NAME
FREQUENCY (MHz)
REMARKS
27
PD75P238
DC CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V) (1/3)
PARAMETER VIH1 VIH2 Input voltage high VIH3 SYMBOL TEST CONDITIONS All ports and pins except those listed below. Port 0, 1, RESET, P81, P83 X1, X2, XT1 VDD = 4.5 to 6.0 V MIN. 0.7 VDD 0.8 VDD VDD -0.4 0.65 VDD 0.7 VDD VIH5 VIL1 Input voltage low VIL2 VIL3 Port 4, 5 Open-drain 0.7 VDD 0 0 0 VDD = 4.5 to 6.0 V IOH = -1 mA VDD -1.0 VDD = 2.7 IOH = to 6.0 V -100 A VDD = 4.5 IOH = 15 mA to 6.0 V VDD = 4.5 IOL = to 6.0 V 1.6 mA VDD = 2.7 IOL = to 6.0 V 400 A Open-drain pull-up resistor 1 k VDD -0.5 0.4 2.0 TYP. MAX. VDD VDD VDD VDD VDD 10 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V V V V
VIH4
Port 7
All ports and pins except those listed below. Port 0, 1, RESET, P81, P83 X1, X2, XT1 All output pins, except port 4, 5 and P03
Output voltage high
VOH
V V
Ports 3, 4, 5
0.4
V
Output voltage low
VOL
All output pins
0.5
V
SB0, SB1
0.2 VDD
V
ILIH1 Input leakage current high ILIH2 ILIH3
All ports and pins except those listed below. X1, X2, XT1 Ports 4, 5 All ports and pins except those listed below. X1, X2, XT1
3 VIN = VDD
A
20 VIN = 10 V 20
A A
Input leakage current low
ILIL1
-3 VIN = 0 V
A
ILIL2
-20
A
28
PD75P238
DC CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V) (2/3)
PARAMETER SYMBOL TEST CONDITIONS All ports and pins except those listed below. Port 4, 5 All ports and pins except those listed below. Display output S0 to S9, S16 to S23 T0 to T15 On-chip pull-down resistor (Mask option) MIN. TYP. MAX. UNIT
Output leakage current high
ILOH1
VOUT = VDD
3
A
ILOH2
VOUT = 10 V
20
A
ILOL1 Output leakage current low ILOL2
VOUT = 0 V
-3
A
VOUT = VLOAD = VDD - 35 V
-10
A
Display output current
IOD
VDD = 4.5 to 6.0 V VOD = VDD - 2 V
-3
-5.5
mA
-15
-22
mA
RL
Display output
VOD - VLOAD = 35 V
25
50
135
k
On-chip pull-up resistor
RV1
Port 0, 1, 2, 3, VDD = 5 V 10% 6 (Except P00) VIN = 0 V VDD = 3 V 10% VDD = 5V 10%*2 VDD = 3 V 10%*3 VDD = 5 V 10% VDD = 3 V 10% VDD = 5 V 10%*2 VDD = 3 V 10%*3 VDD = 5 V 10% VDD = 3 V 10%
15 30
40
80 300
k k
IDDI 6MHz crystal oscillation C1 = C2 = 22 pF*4 IDD2 Power supply current*1
Operating mode
9
18
mA
1
3
mA
900
2700
HALT mode
A A
300
900
IDDI 4.19MHz crystal oscillation C1 = C2 = 22 pF*4
Operating mode
5
15
mA
0.9
2.7
mA
600
1800
A A
IDD2
HALT mode
200
600
* 1. 2. 3. 4.
Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. When the processor clock control register (PCC) is set to 0011 and is operated at high-speed mode. When the PCC register is set to 0000 and is operated in the low-speed mode. Includes the case where the subsystem clock oscillating.
29
PD75P238
DC CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V) (3/3)
PARAMETER SYMBOL TEST CONDITIONS Operating mode HALT mode VDD = 3 V 10% VDD = 3 V 10% MIN. TYP. MAX. UNIT
IDD3
32 kHz crystal oscillation*2
100
300
A
IDD4 Power supply current*1 IDD5 XT1 = 0 V STOP mode
20 0.5 0.3
60 20 10 5
A A A A A
VDD = 5 V 10% VDD = 3 V 10% STOP mode
Ta = 25C VDD = 3 V 10%
IDD6
32 kHz crystal oscillation*2
5
15
* 1. 2.
Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped.
A/D CONVERTER CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, 2.7 AVDD VDD)
PARAMETER Resolution Absolute accuracy*1 Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN -10 Ta +70C -40 Ta < -10C *2 *3 AVSS SYMBOL TEST CONDITIONS MIN. 8 TYP. 8 MAX. 8 1.5 LSB 2.0 168/fX 44/fX AVREF UNIT bit
2.5 V AVREF VDD
s s
V
RAN IAREF
1000 1.0 2.0
M mA
* 1. 2. 3.
Absolute accuracy except quantization error (1/2 LSB). Time from execution of conversion start instruction to EOC = 1 (28.0 s when fX = 6.0 MHz, 40.1 s when fX = 4.19 MHz) Time from execution of conversion start instruction to the end of sampling (7.33 s when fX = 6.0 MHz, 10.5 s when fX = 4.19 MHz)
30
PD75P238
AC CHARACTERISTICS (Ta = -40 to +70 C, VDD = 2.7 to 6.0 V) (1) Basic Operation
PARAMETER CPU clock cycle time (minimum instruction execution time = one machine cycle)*1 SYMBOL TEST CONDITIONS Operation with main system clock VDD = 4.75 to 6.0 V MIN. TYP. MAX. UNIT
0.67 2.6
64 64 122 125 1 275
s s s
MHz kHz
tCY
Operation with subsystem clock VDD = 4.5 to 6.0 V TI0 input frequency fTI
114 0 0
TI0 input high and low-level widths Interrupt input high and low-level widths RESET low level widths
tTIH, tTIL
VDD = 4.5 to 6.0 V
0.48 1.8
s s s s s
tINTH, tINTL
INT0 INT1, 2, 4
*2 10 10
tRSL
* 1. CPU clock () cycle time is determined by the oscillator for frequency of the connected oscillator, the system clock control register (SCC) and processor clock control register (PCC). The cycle time tCY characteristics for supply voltage VDD when the main system clock is in operation is shown on the right. 2. 2tCY or 128/fX is set by interrupt mode register (IM0) setting.
70 64 60 6 5 4
tcy vs VDD (When main system clock is in operation)
Operation Guaranteed Range
Cycle Time tcy [s]
3
2
1
0.5 0 1 2 3 4 5 6
Power Supply Voltage VDD [V]
31
PD75P238
(2) Serial Transfer Operation (a) 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output)
PARAMETER SYMBOL TEST CONDITIONS fX = 6.0 MHz fX = 4.19 MHz fX = 6.0 MHz fX = 4.19 MHz VDD = 4.5 to 6.0 V SCK high and low level widths tKL1 tKH1 MIN. 1340 1600 2680 3800 (tKCY1/2) -50 (tKCY1/2) -150 150 TYP. MAX. UNIT ns ns ns ns ns
VDD = 4.5 to 6.0 V SCK cycle time tKCY1
ns
SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK
tSIK1
ns
tKSI1 VDD = 4.5 to 6.0 V
400
ns
tKSO1
RL = 1 k , CL = 100 pF*
250 1000
ns ns
* RL and CL denote load resistor and load capacitance of SO output line. (b) 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tSIK2
tKSI2 VDD = 4.5 to 6.0 V
400
ns
tKSO2
RL = 1 k , CL = 100 pF*
300 1000
ns ns
* RL and CL denote load resistor and load capacitance of SO output line.
32
PD75P238
(c) SBI Mode (SCK ... Internal clock output (Master))
PARAMETER SYMBOL TEST CONDITIONS fX = 6.0 MHz VDD = 4.5 to 6.0 V fX = 4.19 MHz SCK cycle time tKCY3 fX = 6.0 MHz fX = 4.19 MHz SCK high and low level widths SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low level widths SB0, 1 high level widths tKL3 tKH3 VDD = 4.5 to 6.0 V 2680 3800 tKCY3/2-50 tKCY3/2-150 150 ns ns ns ns ns 1600 ns MIN. 1340 TYP. MAX. UNIT ns
tSIK3
tKSI3 RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V
tKCY3/2 0 0 250 1000
ns ns ns ns ns ns
tKSO3
tKSB tSBK tSBL
tKCY3 tKCY3 tKCY3
tSBH
tKCY3
ns
* RL and CL denote load resistor and load capacitance of SO output lines.
33
PD75P238
(d) SBI Mode (SCK ... External clock input (Slave))
PARAMETER SCK cycle time tKCY4 SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 3200 SCK high and low level widths tKL4 tKH4 VDD = 4.5 to 6.0 V 400 1600 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK tSIK4 100 TYP. MAX. UNIT ns ns ns ns ns
tKSI4 VDD = 4.5 to 6.0 V
tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns
tKSO4
RL = 1 k CL = 100 pF*
SB0, 1 from SCK tKSB SCK from SB0, 1 tSBK SB0, 1 low level widths SB0, 1 high level widths tSBL
tSBH
tKCY4
ns
* RL and CL denote load resistor and load capacitance of SO output lines.
34
PD75P238
AC Timing Test Points (Except X1 and XT1 Inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timings
1/fX tXL tXH
X1 Input
VDD -0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD -0.5 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
35
PD75P238
Serial Transfer Timing 3-wired serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI tKSO1
Input Data
SO
Output Data
2-wired serial I/O mode:
tKCY2 tKL2 tKH2
SCK tSIK2
tKSO2
tKSI2
SB0,1
36
PD75P238
Serial Transfer Timing Bus release signal transfer:
tKCY3,4 tKH3,4
tKL3,4
SCK tSIK3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1 tKSO3,4
Command signal transfer:
tKL3,4
tKCY3,4 tKH3,4
SCK tSIK3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4
RESET Input Timing
tRSL
RESET
37
PD75P238
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to 70 C)
PARAMETER Data retention power supply voltage Data retention power supply current*1 Release signal set time Oscillation stabilization wait time*2 SYMBOL VDDDR TEST CONDITIONS MIN. 2.0 TYP. MAX. 6.0 UNIT V
IDDDR
VDDDR = 2.0 V
0.1
10
A s
tSREL Release by RESET tWAIT Release by interrupt request
0 217/fx *3
ms ms
* 1. 2. 3.
Current to the on-chip pull-up resistor and power-on reset circuit (mask option) is not included. Oscillation stability wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM). (see below)
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1 2 /fx (approx. 175 ms) 217/fx (approx. 21.8 ms) 215/fx (approx. 5.46 ms) 213/fx (approx. 1.37 ms)
20
Wait Time Values at fX = 6.0 MHz in Parentheses Values at fX = 4.19 MHz in Parentheses 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms)
38
PD75P238
Data Retention Timing (STOP mode release by RESET)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
39
PD75P238
DC PROGRAMMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Input voltage high VIH1 VIH2 VIL1 VIL2 ILI SYMBOL TEST CONDITIONS Except X1 and X2 X1, X2 Except X1 and X2 X1, X2 VIN = VIL or VIH MIN. 0.7 VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 UNIT V V V V
Input voltage low Input leakage current Output voltage high Output voltage low VDD supply current VPP supply current
A
VOH
IOH = -1 mA
VDD -1.0
V
VOL IDD IPP
IOH = 1.6 mA
0.4 30
V mA mA
MD0 = VIL, MDI =VIH
30
Note
1. VPP, including overshoot, should not exceed +13.5 V. 2. VDD should be applied before VPP and cut after VPP.
AC PROGRAMMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) (1/2)
PARAMETER Address setup time*2 (to MD0 ) MD1 setup time (to MD0 ) Data setup time (to MD0 ) Address hold time*2 (from MD0 ) Data hold time (from MD0 ) Data output float delay time from MD0 VPP setup time (to MD3 ) VDD setup time (to MD3 ) SYMBOL tAS tM1S tDS tAH tAS tOES tDS tAH *1 TEST CONDITIONS MIN. 2 2 2 2 TYP. MAX. UNIT
s s s s s
tDH
tDH
2
tDF tVPS tVDS
tDF tVPS tVCS tPW tOPW tCES tDV MD0 = MD1 = VIL
0 2 2 0.95 0.95 2 1.0
130
ns
s s
1.05 21.0 ms ms
Initial program pulse widths tPW Additional program pulse widths MD0 setup time (to MD1 ) Data output delay time from MD0 tOPW tMOS tDV
s
1
s
* 1. 2. 40
The corresponding PD27C256 symbol. Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the pin.
PD75P238
AC PROGRAMMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) (2/2)
PARAMETER MD1 hold time (from MD0 ) MD1 recovered time (to MD0 ) Program counter reset time X1 input high and low level widths X1 input frequency Initial mode set time MD3 setup time (to MD1 ) MD3 hold time (from MD1 ) MD3 setup time (to MD0 ) SYMBOL tM1H *1 tOEH tM1H + tM1R 50 s tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tACC When reading program memory When reading program memory 2 2 2 2 2 tOR 2 10 0.125 4.19 TEST CONDITIONS MIN. 2 TYP. MAX. UNIT
s s s s
MHz
s s s s s
Data output delay time from tDAD address*2 Data output hold time from address*2 MD3 hold time (from MD0) Data output float delay time from MD3 tHAD
tOH
When reading program memory
0
130
ns
tM3HR
When reading program memory
2
s s
tDFR
When reading program memory
2
* 1. 2.
The corresponding PD27C256 symbol. Internal address signal is incremented by one on the rise of fourth X1 input and is not connected to the pin.
41
PD75P238
Write Timing of Program Memory
tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH
X1 tXL Input Data tDS tDH tAH tAS Input Data
P40 to P43 P50 to P53 tI MD0
Input Data tDS tOH
Output Data
tDV
tDF
tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H
tM1R
tMOS
tOPW
tM3H
Read Timing of Program Memory
tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH
X1 tXL tHAD P40 to P43 P50 to P53 tI MD0 tDV Output Data Output Data tM3HR tDFR tDAD
MD1 tPCR MD2 tM3SR MD3
42
PD75P238
7. PACKAGE INFORMATION
94 PIN PLASTIC QFP (
20)
A B
F2
71 72
48 47 detail of lead end
D
C
S
94 1
24 23
F1
G1
G2 H IM J K
P
N
L S94GJ-80-5BG-2 ITEM A B C D F1 F2 G1 G2 H I J K L M N P Q S MILLIMETERS 23.2 0.4 20.0 0.2 20.0 0.2 23.2 0.4 1.6 0.8 1.6 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.6 0.2 0.8 0.2 0.15 +0.10 -0.05 0.12 3.7 0.1 0.1 4.0 MAX. INCHES 0.913+0.017 -0.016 0.787+0.009 -0.008 0.787+0.009 -0.008 0.913+0.017 -0.016 0.063 0.031 0.063 0.031 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.063 0.008 0.031-0.008 0.006 0.005 0.146 0.004 0.004 0.158 MAX.
+0.004 -0.003 +0.009
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
55
Q
43
PD75P238
94 PIN CERAMIC WQFN
A B K Y
T
D
C
94
W
Q
U
H
I
M
1 R
J
E F G
X94KW-80A-1
NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K Q R S T U W
MILLIMETERS 20.0 0.4 18.0 18.0 20.0 0.4 1.94 2.14 4.064 MAX. 0.51 0.10 0.08 0.8 (T.P.) 1.0 0.2 C 1.0 1.6 1.6 R 1.75 11.5 0.75 0.2
INCHES 0.787+0.017 -0.016 0.709 0.709 0.787+0.017 -0.016 0.076 0.084 0.160 MAX. 0.020 0.004 0.003 0.031 (T.P.) 0.039 -0.008 C 0.039 0.063 0.063 0.069 0.453 0.030 -0.009
+0.008 +0.009
44
S
PD75P238
8. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 8-1 Surface Mount Type Soldering Conditions
5
PD75P238GJ-xxx-5BG : 94-pin plastic QFP (s 20 mm) s
Recommended Condition Symbol IR30-107-1
Soldering Method
Soldering Conditions Package peak temperature: 230 C, Duration: 30 sec. max. (at 210 C or above); Number of times: Once, Time limit: 7 days* (125 C prebaking requires 10 hours thereafter) Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above); Number of times: Once, Time limit: 7 days* (125 C prebaking requires 10 hours thereafter) Pin part temperature: 300 C max.; Duration: 3 sec. max., (per device side)
Infrared reflow
VPS Pin part heating
VP15-107-1
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25 C, 65% RH.
Note Use of more than one soldering method should be avoided (except in the case of pin part heating).
45
PD75P238
APPENDIX A. DEVELOPMENT TOOLS
The following support tools are available for system development using the PD75P238.
IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 Hardware EP-75238GJ-R EV-9200G-94 PG-1500 PA-75P238GJ PA-75P238KF Softwar IE control program PG-1500 controller RA75X relocatable assembler 75X series in-circuit emulator IE-75000-R/IE-75001-R emulation board
PD75P238 emulation probe 94-pin conversion socket EV-9200G-94 is provided
PROM programmer PG-1500 connected with PD75P238GJ PROM program adapter PG-1500 connected with PD75P238KF PROM program adapter Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3) IBM PC/ATTM (PC DOSTM Ver.3.1)
* 1. Maintenance product 2. Not incorporated in IE-75001-R 3. The task swap function, which is provided with Ver.5.00/5.00A. is not available with this software. Remarks For development tools manufactured by a third party, see the "75X Series Selection Guide" (IF-151).
46
PD75P238
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual Instruction Application Table 75X Series Selection Guide Document No.
5
Development Tools Related Documents
Document Name IE-75000-R/IE-75001-R User's Manual Software Hardware IE-75000-R-EM User's Manual EP-75238GJ-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Volume Language Volume Document No.
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Document No.
Note
The contents of the above related documents are subjected to change without notice. The latest documents should be used for design, etc.
47
PD75P238
48
PD75P238
49
PD75P238
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
FIP is a trademark of NEC Corporation. MS-DOS is a trademark of MicroSoft Corporation. PC DOS, PC/AT are trademarks of IBM Corporation.

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